Senior Analog IC Layout Engineer Permanent

Reporting to the Analog Design Manager, this position is expected to manage the analog physical layout implementation taking care of the chip floorplanning, analog blocks layout, and physical verification of the CMOS image sensors designed by the team.

The candidate needs to have a basic but solid expertise in analogue and mixed-signal IC design, with understanding of common mixed-signal blocks (A/D converters, voltage/current references, bandgaps, amplifiers, PLLs, etc.). Know-how in CMOS image sensors is a benefit.

Expertise in full-custom layout using deep-submicron technologies (40nm CMOS or below), with comprehensive knowledge of the layout effects on device behaviour and impact on circuit performance is required. Experience in physical verification (DRC, LVS) using EDA tools from the main vendors such as Cadence, Synopsys, or MentorGraphics, is also needed.

She/he will work with cross-functional and multi-cultural teams (e.g. digital design team, analog design team, architecture team), following the EUTDC design methodology. Periodical reporting, design reviews, participation to internal seminars and training are part of the activity.

Experience in image sensor pixel layout design and/or use of 3D stacking technology is a plus. In addition, a good knowledge of the modern CMOS fabrication processes is preferred, also including CMOS image sensor processes